A semiconductor device such as a DRAM (Dynamic Random-Access Memory) sometimes includes a parallel to serial conversion circuit that converts parallel read data into serial data, and a serial to parallel conversion circuit that converts serial write data into parallel data. The parallel to serial conversion circuit performs a parallel to serial conversion operation in synchronization with read clock signals different in phase from one another, and the serial to parallel conversion circuit performs a serial to parallel conversion operation in synchronization with write clock signals different in phase from one another. Because the frequency of data serially output from the parallel to serial conversion circuit is high, it is desirable to reduce the resistance of the output node as much as possible.